Table of content
Lecture by Professor Dinesh Sharma
Intoduction to VHDL
Structural description
Structural description of Full Adder
Full Adder Testbench
Behavioural description (Part-1)
Behavioural description (Part-2)
Quartus Design Flow
#(NOTE: IN “FAMILY, DEVICE AND BOARD SETTINGS” STEP, SELECT THE DEVICE FAMILY AS MAX 10(DA/DF/DC/SA/SC) AND IN THE NAME FILTER, TYPE - 10M25SAE144C8G)