EE214

NPTEL - Digital Systems (Krypton CPLD based)

Day	Date	Topic	Lab Material	Handouts
Day - 0	-	Pre-Workshop	Introduction to VHDL by Prof. Dinesh Sharma 📽 Structural Description by Prof. Dinesh Sharma 📽 Structural description of Full Adder by Prof. Dinesh Sharma 📽 Full Adder Testbench by Prof. Dinesh Sharma 📽 VHDL_by_Peter_J_Ashenden.pdf 📃 Quartus Design Flow 📽 Lab Manual 📖 Full Adder Demo Resources 📁 Tracefile Generation 📁 Using Quartus for project generation and simulation Max V Device support installation
Day - 1	5th June	Introductory Session	Quartus Design Flow 📽	AND, XOR using Universal Gates HW- 4-Bit Adder-Subtractor
Day - 2	6th June	Introduction to VHDL and Structural Description by Prof. Virendra Singh		Multiplexers HW- Decoders
Day - 3	7th June	CPLD/FPGA Technology by Prof. Virendra Singh Krypton Board Introduction	UrJTAG Installation Files (Windows) UrJTAG Installation Files (Ubuntu) Krypton Drivers White_Krypton_Test_Files Blue_Krypton_Test_Files Using UrJTAG and Krypton (slides) altera.zip	4- Bit Adder-Subtractor Barrel Shifter HW- Prime Detector
Day - 4	8th June	Session on Scan Chain	Scanchain (Presentation) Scanchain Demo Video Scanchain Files scan-25k.svf Python and Pip installation guide (Windows)	Mux Verification using Scan Chain Decoder Verification using Scan Chain
Day - 5	9th June	Behavioural Hardware Description by Prof. Virendra Singh Quiz	Behavioural Description by Prof. Dinesh Sharma (Part-1) 📽 Behavioural Description by Prof. Dinesh Sharma (Part-2) 📽	Quiz Problem Satement
Weekend
Day - 6	12th June			BCD Addition Fibbonacci Detector
Day - 7	13th June	Lecture on FSM by Prof. Virendra Singh	VHDL Functions PPT VHDL Functions Demo Video 📽	ALU HW- ALU
Day - 8	14th June			Sequence Generator Sequence Detector HW- Sequence Detector
Day - 9	15th June	Mini-Project
Day - 10	16th June	Mini-Project